Minimum run-changing point mark coding compression method
ZHAN Wenfa1,2, TAO Pengcheng1,2
1. School of Computer and Information, Anqing Normal University, Anqing 246003, China; 2. Key Laboratory of Intelligent Sensing and Computing in Anhui Province, Anqing 246003, China
Abstract：Integrated circuit testing produces huge quantities of test data in expensive tests. This paper describes use of the minimum run-changing point mark coding compression method to compress the original test data to reduce the test costs. The method encodes the test set into several vectors and uses the overlapping relationships between the vector run range in each group to merge the run-length switching points. The run position in all the test vectors in the group can be represented by a vector which simplifies traditional coding compression. The method breaks through the limitation of using the suffix of the code word to express the length of the run, and greatly shortens the code word compared to conventional code compression. The method has simple decompression rules and low hardware overhead. Tests with the ISCAS 89 standard circuit experiment show that this compression scheme is more effective than other types of coding compression schemes.
[1] 陈田, 易鑫, 王伟, 等. 一种低功耗双重测试数据压缩方案[J]. 电子学报, 2017, 45(6):1382-1388.CHEN T, YI X, WANG W, et al. Low power multistage test data compression scheme[J]. Acta Electronica Sinica, 2017, 45(6):1382-1388. (in Chinese) [2] XIANG D, CHAKRABARTY K, FUJIWARA H. Multicast-based testing and thermal-aware test scheduling for 3D ICs with a stacked network-on-chip[J]. IEEE Transactions on Computers, 2016, 65(9):2767-2779. [3] LIANG H G, FANG X S, YI M X, et al. A novel BIST scheme for circuit aging measurement of aerospace chips[J]. Chinese Journal of Aeronautics, 2018, 31(7):1594-1601. [4] YU T T, CUI A J, LI M Y, et al. A new decompressor with ordered parallel scan design for reduction of test data and test time[C]//2015 IEEE International Symposium on Circuits and Systems. Lisbon, Portugal:IEEE, 2015. [5] 袁海英, 陈光, 谢永乐. 故障诊断中基于神经网络的特征提取方法研究[J]. 仪器仪表学报, 2007, 28(1):90-94.YUAN H Y, CHEN G J, XIE Y L. Feature extraction method in fault diagnosis based on neural network[J]. Chinese Journal of Scientific Instrument, 2007, 28(1):90-94. (in Chinese) [6] 詹文法, 吴琼, 程一飞, 等. 嵌入广义折叠技术的集成电路测试数据压缩方案[J]. 计算机辅助设计与图形学学报, 2017, 29(8):1542-1548.ZHAN W F, WU Q, CHENG Y F. et al. Integrated circuit test data compression scheme built-in generalized folding technology[J]. Journal of Computer-Aided Design & Computer Graphics, 2017, 29(8):1542-1548. (in Chinese) [7] 李光宇, 梁华国, 李扬, 等. 基于向量优化重组的LFSR重新播种方法[J]. 清华大学学报(自然科学版), 2011, 51(S1):1455-1459.LI G Y, LIANG H G, LI Y, et al. LFSR reseeding based on dividing and recombining of test cubes[J]. Journal of Tsinghua University (Science and Technology), 2011, 51(S1):1455-1459. (in Chinese) [8] VOHRA H, SINGH A. Test data compression using hierarchical block merging technique[J]. Iet Computers & Digital Techniques, 2018, 12(4):176-185. [9] RADHIKA K, GEETHA D M. Augmented recurrence hopping based run-length coding for test data compression applications[J]. Wireless Personal Communications, 2018, 102(4):3361-3374. [10] CHANDRA A, CHAKRABARTY K. System-on-a-chip test-data compression and decompression architectures based on Golomb codes[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 20(3):355-368. [11] CHANDRA A, CHAKRABARTY K. Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes[J]. IEEE Transactions on Computers, 2003, 52(8):1076-1088. [12] 邝继顺, 周颖波, 蔡烁. 一种用于测试数据压缩的自适应EFDR编码方法[J]. 电子与信息学报, 2015, 37(10):2529-2535.KUANG J S, ZHOU Y B, CAI S. Adaptive EFDR coding method for test data compression[J]. Journal of Electronics & Information Technology, 2015, 37(10):2529-2535. (in Chinese) [13] 梁华国, 蒋翠云. 基于交替与连续长度码的有效测试数据压缩和解压[J]. 计算机学报, 2004, 27(4):548-554.LIANG H G, JIANG C Y. Efficient test data compression and decompression based on alternation and run length codes[J]. Chinese Journal of Computers, 2004, 27(4):548-554. (in Chinese) [14] GONCIARI P T, AL-HASHIMI B M, NICOLICI N. Variable-length input Huffman coding for system-on-a-chip test[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003, 22(6):783-796. [15] TEHRANIPOOR M, NOURANI M, CHAKRABARTY K. Nine-coded compression technique for testing embedded cores in SoCs[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, 13(6):719-731. [16] 韩银和, 李晓维, 徐勇军, 等. 应用Variable-Tail编码压缩的测试资源划分方法[J]. 电子学报, 2004, 32(8):1346-1350.HAN Y H, LI X W, XU Y J, et al. Test resource partitioning using variable-tail code[J]. Acta Electronica Sinica, 2004, 32(8):1346-1350. (in Chinese) [17] 彭喜元, 俞洋. 基于变游程编码的测试数据压缩算法[J]. 电子学报, 2007, 35(2):197-201.PENG X Y, YU Y. A test set compression algorithm based on variable-run-length code[J]. Acta Electronica Sinica, 2007, 35(2):197-201. (in Chinese) [18] RUAN X Y, KATTI R. An efficient data-independent technique for compressing test vectors in systems-on-a-chip[C]//IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures. Karlsruhe, Germany:IEEE, 2006. [19] 方建平, 郝跃, 刘红侠, 等. 应用混合游程编码的SOC测试数据压缩方法[J]. 电子学报, 2005, 33(11):1973-1977.FANG J P, HAO Y, LIU H X, et al. A hybrid run-length coding for SOC test data compression[J]. Acta Electronica Sinica, 2005, 33(11):1973-1977. (in Chinese) [20] 梁华国, 蒋翠云, 罗强. 应用对称编码的测试数据压缩解压方法[J]. 计算机研究与发展, 2011, 48(12):2391-2399.LIANG H G, JIANG C Y, LUO Q. Test data compression and decompression using symmetry-variable codes[J]. Journal of Computer Research and Development, 2011, 48(12):2391-2399. (in Chinese) [21] 程一飞, 詹文法. 一种双游程交替编码的测试数据压缩方法[J]. 计算机科学, 2014, 41(11):22-24, 55.CHENG Y F, ZHAN W F. Test data compression method of dual run length alternating coding[J]. Computer Science, 2014, 41(11):22-24, 55. (in Chinese)
2020, Vol. 60 
