Multi-rate LDPC encoder for high-speed satellite data transmissions

doi:10.16511/j.cnki.qhdxxb.2016.22.028

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Abstract Satellite data transmission systems need high coding gains, multiple rates and high reliability channel coding. A low complexity, high speed encoder is designed for low-density parity-check (LDPC) codes, which reduces the hardware size and improves the encoding speed and reliability. The system reuses hardware resources for codes of various rates and lengths and uses a low-storage architecture and a partially triple-modular-redundant design scheme. Field programmable gate array (FPGA) synthesized results show that the encoder integrates 28 codes with aerospace reinforcement and a maximum encoding speed of 3.2 Gb/s in a Xilinx XC2V3000 FPGA chip. The flip-flop, look-up table (LUT) and RAM costs of the encoder are 24.5%, 34.4% and 11.1% less than that for the traditional scheme. This encoder design scheme will improve satellite data transmission systems.

Keywords low-density parity-check (LDPC) codes high-speed encoder design multi-rate integrated low-complexity satellite data transmission

ZTFLH:

TN919.3

Issue Date: 15 June 2016

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	GE Guangjun
	YIN Liuguo

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GE Guangjun,YIN Liuguo. Multi-rate LDPC encoder for high-speed satellite data transmissions[J]. Journal of Tsinghua University(Science and Technology), 2016, 56(6): 656-660.

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http://jst.tsinghuajournals.com/EN/10.16511/j.cnki.qhdxxb.2016.22.028 OR http://jst.tsinghuajournals.com/EN/Y2016/V56/I6/656

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