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Design and implementation of a side-channel resistant and low power RSA processor |
| REN Yanting1,2, WU Liji1,2, LI Xiangyu1,2, WANG An1,2, ZHANG Xiangmin1,2 |
1. Institute of Microelectronics, Tsinghua University, Beijing 100084, China;
2. Tsinghua National Laboratory for Information Science and Technology, Beijing 100084, China |
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Abstract RSA is the most widely used public-key algorithm, and is specified as the signature algorithm in bank IC cards. The unprotected RSA implementation is vulnerable to side-channel attacks as pointed out in several works. Due to the complexity of the algorithm, the power consumption of an RSA module is usually high. A side-channel resistant, efficient and low-power RSA processor was designed using countermeasures against side-channel attacks based on the Montgomery ladder with a modified Montgomery algorithm then proposed, which combines CIOS and Karatsuba algorithms. The computation time of modular multiplication can be reduced by 25% with the length of RSA being configurable and up to 2 048 bits. The proposed RSA module was verified with C*Core C0 in FPGA board. With SMIC 0.13 μm CMOS process, the EDA synthesis result indicates that the area is about 24 000 gates, and the throughput of 1024-bit RSA is 8.3 kb/s under the frequency of 30 MHz with the power consumption of 1.15 mW.
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| Keywords
RSA
low-power
side-channel attack
Montgomery algorithm
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Issue Date: 15 January 2016
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2016,
Vol. 56
