Scan segmentation test architecture for power controllability

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Abstract As chip sizes reach micro-nano levels, the increasing power consumption during chip testing is becoming a bottleneck for chip production and testing. Prior work has mainly focused on reducing the power dissipation in either the shift cycle or the capture cycle with little work on reducing the peak power for both the shift and capture cycles at the same time. Moreover, there has been no work on the capture power controllability. This paper presents a power-aware scan segment architecture which controls the power during the shift and capture cycles at the same time with small area overhead. Meanwhile, the dependency checking and scan segment partitioning algorithms directly reduce the switching activity of flip-flops by iteratively optimizing the scan segment grouping. This method analyzes the power controllability in terms of both the structure dependency and the clock tree impact. Tests on reference circuits ISCAS89 and IWLS2005 verify the effectiveness of this architecture.

Keywords scan testing scan segmentation power-aware testing controllable capture cycle design for testability

ZTFLH:

TP331.2

Issue Date: 15 August 2015

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	JIANG Zhou
	XIANG Dong
	SHEN Kele

Cite this article:

JIANG Zhou,XIANG Dong,SHEN Kele. Scan segmentation test architecture for power controllability[J]. Journal of Tsinghua University(Science and Technology), 2015, 55(8): 889-894.

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http://jst.tsinghuajournals.com/EN/ OR http://jst.tsinghuajournals.com/EN/Y2015/V55/I8/889

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