当前已有研究发明了一种新的有限域快速Fourier变换，即Lin-Chung-Han fast fourier transform(LCH-FFT)，并将其应用于Reed-Solomon(RS)码。该文基于LCH-FFT，提出RS码的高效编译码算法与架构。编码方面，基于LCH-FFT设计了2种新的RS码系统编码器架构：通过改进现有的编码算法设计而成的Ⅰ型编码器，通过提出一种新的纠删译码算法设计而成的Ⅱ型编码器。译码方面，基于LCH-FFT设计了一种新的RS码译码器的架构，且在关键方程求解模块根据最新提出的频域模方法(frequency-domain modular approach，FDMA)算法设计了一种脉动阵列架构。由此证明了基于LCH-FFT的RS编译码算法和架构经过简单处理后，可适用于常用的循环RS码。基于现场可编程门阵列(field-programmable gate array，FPGA)完成了RS(544, 514)码编译码器的硬件设计，结果表明基于LCH-FFT的RS编译码器相比传统编译码器具有更显著的资源优势。

Objective: Reed-Solomon (RS) codes represent a category of error-correction codes that have been extensively used in various communication and storage systems. However, in some applications, such as optical transmission, very high transmission rates cause several challenges for the efficient implementation of codecs, especially for low-power performance. Methods: The conventional approach of employing a parallel configuration for both the encoder and decoder lacks efficiency. The fast Fourier transform (FFT) over finite fields can be utilized to reduce the decoding complexity of RS codes. Recently, Lin, Chung, and Han developed a novel FFT that, for the first time, attains the O(nlogn) complexity (n is the FFT size) for binary extension fields. An LCH-FFT-based encoding algorithm with complexity O(nlogk) was presented for an (n, k) RS code when $ \frac{k}{n}$ ≤0.5 and k is a power of 2. An LCH-FFT-based erasure decoding algorithm was developed with complexity O(nlogn). The erasure-decoding algorithm is applicable to both low-rate and high-rate RS codes. LCH-FFT was also applied to the error decoding of the RS codes. A novel LCH-FFT-based encoding algorithm with complexity O(nlog(n-k)) was presented for an (n, k) RS code when $ \frac{k}{n}$ ≥0.5 and n-k is a power of 2. The key equation was derived and solved using the extended Euclidean algorithm. It has been demonstrated that the complexity O(nlog(n-k)+(n-k)log²(n-k)) is achieved. A variant of the LCH-FFT algorithm, designated as the partial FFT algorithm, was introduced to adapt to general code parameters. More recently, Tang and Han proposed the use of the Welch-Berlekamp approach for the resolution of the key equation. A novel variant, designated as the modular approach (MA) algorithm, was derived. Subsequently, the frequency-domain modular approach (FDMA) algorithm and the fast modular approach (FMA) algorithm were developed on this basis, exhibiting a complexity of O(nlog(n-k)+(n-k)log²(n-k)). The LCH-FFT-based decoding method exhibits a significantly lower degree of complexity compared to alternative decoding methodologies for RS codes. Existing works have demonstrated that LCH-FFT-based encoding and decoding achieve complexity advantages over the commonly used LFSR-based encoding and syndrome-based decoding. The implementation of a low-complexity algorithm in hardware may not be feasible. Consequently, the investigation of the implementation aspects of the LCH-FFT-based encoding and decoding methods is of practical interest. The RS codes for which the LCH-FFT-based coding methods were developed are based on the polynomial evaluation method. However, most of the RS codes in use are of the shortened cyclic code variety, which are constructed as a specific class of BCH codes based on the generator polynomial of a cyclic code. Therefore, it is worthwhile to investigate the applicability of LCF-FFT coding methods to RS codes based on the BCH construction. Such a determination is important for standardized RS codes, for which the definition has been established. Results: To address these issues, the present study proposes new algorithms and architectures for RS codes based on the LCH-FFT. Two types of systematic encoders have been developed. The Type-Ⅰ encoder is obtained by modifying a known encoding algorithm. The development of a novel erasure decoding algorithm has enabled the creation of a new encoding algorithm, which forms the foundation for the design of a Type-Ⅱ encoder. The decoder architecture has been designed based on LCH-FFT. For the key equation solver (KES) block in the decoder, a systolic architecture is designed based on the FDMA algorithm recently proposed by Tang and Han. The LCH-FFT-based en/decoding devices designed for polynomial-evaluation-based RS codes are also applicable to commonly used cyclic RS codes through the incorporation of straightforward pre- and post-processing methodologies. Conclusions: FPGA-based emulation demonstrates that the LCH-FFT-based RS encoder and decoder can achieve significant advantages in terms of resource consumption compared to the conventional implementation.