Wear-leveling method for PCM based on random mapping

LIU Wei; WANG Yuping

doi:10.16511/j.cnki.qhdxxb.2015.21.005

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Journal of Tsinghua University(Science and Technology) ›› 2015, Vol. 55 ›› Issue (11) : 1208-1215. DOI: 10.16511/j.cnki.qhdxxb.2015.21.005

COMPUTER SCIENCE AND TECHNOLOGY

Wear-leveling method for PCM based on random mapping

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Abstract

Phase change memory(PCM) uses a phase change material that is non-volatile, higher density, lower energy, and has better scalability than other methods. The main problem with PCM materials is the cell write limitation. Recent studies have focused on optimizing the write operations and wear-leveling, but cannot prevent malicious attacks to rapidly wear the PCM cells. This paper presents a PCM wear-leveling method which divides the whole PCM memory into two levels with separate random mapping tables to convert the logical cell addresses into physical addresses. The random mapping tables are updated dynamically according to the write count thresholds. This method not only implements PCM wear-leveling, but also resists malicious wearing-out attacks. Tests show that This method improves the wear-leveling by up to 87.5% over three existing wear-leveling methods with a system performance loss of less than 6% and additional storage overhead of less than 1‰ of the whole memory size.

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operating system / wear-leveling / phase change memory / random mapping

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LIU Wei, WANG Yuping. Wear-leveling method for PCM based on random mapping[J]. Journal of Tsinghua University(Science and Technology). 2015, 55(11): 1208-1215 https://doi.org/10.16511/j.cnki.qhdxxb.2015.21.005

References

[1] Bedeschi F, Fackenthal R, Resta C, et al. A multi-level-cell bipolar-selected phase-change memory[C]//Proceedings of the Solid-State Circuits Conference 2008(ISSCC 2008), Digest of Technical Papers, IEEE International. San Francisco, CA, USA:IEEE press, 2008:428-625.
[2] Papandreou N, Pozidis H, Mittelholzer T, et al. Drift- tolerant multilevel phase-change memory[C]//Memory Workshop(IMW), 2011 3rd IEEE International. Monterey, CA, USA:IEEE press, 2011:1-4.
[3] Raoux S, Burr G W, Breitwisch M J, et al. Phase-change random access memory:A scalable technology[J]. IBM journal of research and development, 2008, 52(4/5):465-479.
[4] Shin D J, Park S K, Kim S M, et al. Adaptive page grouping for energy efficiency in hybrid PRAM-DRAM main memory[C]//Proceedings of the 2012 ACM Research in Applied Computation Symposium(RACS'12). New York, NY, USA:ACM, 2012:395-402.
[5] Yang B D, Lee J E, Kim J S, et al. A low power phase-change random access memory using a data- comparison write scheme[C]//Proceedings of IEEE International Symposium on Circuit and Systems(ISCAS 2007). New Orleans, LA, USA:IEEE press, 2007:3014-3017.
[6] Yang B D, Lee J E, Kim J S, et al. Flip-N-Write:A simple deterministic technique to improve PRAM write performance, energy and endurance[C]//Proceedings of the 42nd Annual International Symposium on Microarchitecture(MICRO-42). New York, NY, USA:IEEE press, 2009:347-357.
[7] Stan M R, Burleson W P. Bus-invert coding for low-power I/O[J]. IEEE transactions on very large scale integration(VLSI) systems, IEEE transactions on, 1995, 3(1):49-58.
[8] Zhou P, Zhao B, Yang J, et al. A durable and energy efficient main memory using phase change memory technology[C]//Proceedings of the International Symposium on Computer Architecture(ISCA'09). New York, NY, USA:ACM, 2009:14-23.
[9] Qureshi M K, Karidis J, Franceschini M, et al. Enhancing lifetime and security of phase change memories via start-gap wear leveling[C]//Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture(MICRO 42). New York, NY, USA:ACM, 2009:14-23.
[10] Seong N H, Woo D H, Lee H H S. Security refresh:Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping[C]//Proceedings of the 37th Annual International Symposium on Computer architecture(ISCA'10). Saint-Malo, France:ACM, 2010:383-394.
[11] Knuth D E. Seminumerical algorithms. The Art of Computer Programming 2[M]. Boston, MA, USA:Addison-Wesley, 1969.
[12] Binkert N, Beckmann B, Black G, et al. The gem5 simulator[J]. ACM SIGARCH computer architecture news, 2011, 39(2):1-7.