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清华大学学报(自然科学版)  2014, Vol. 54 Issue (2): 197-201    
  论文 本期目录 | 过刊浏览 | 高级检索 |
基于FPGA的高精度正弦信号发生器设计与实现
彭卓1,2,邓焱1(),马骋1,熊剑平1,尹永利2
2. 中国航天员科研训练中心, 北京 100094
FPGA based high precision sinusoidal signal generator
Zhuo PENG1,2,Yan DENG1(),Cheng MA1,Jianping XIONG1,Yongli Yin2
1. State Key Laboratory of Precision Measurement Technology and Instruments, Department of Precision Instruments, Tsinghua University, Beijing 100084, China
2. Astronaut Center of China, Beijing 100094, China
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摘要 

地震数据采集系统自检时需要总谐波失真小于 -106 dB的高保真正弦信号,一般采用24位ΔΣ数模转换器来产生,关键技术是如何生成驱动ΔΣ数模转换器的位流。该文提出一种由正弦数据存储器、插值滤波器和ΔΣ调制器组成的位流生成器,重点介绍了插值滤波器和ΔΣ调制器的设计思路、仿真方法及其在现场可编程门阵列(FPGA)中借助DSP Builder工具实现的方法。实测结果表明: 该位流生成器可以驱动一块ΔΣ数模转换器产生31.25 Hz、 峰峰值3.96 V的高保真正弦信号,信噪比达到111.4 dB, 总谐波失真达到-121.0 dB, 满足地震数据采集系统自检的要求,并且具有结构简单、可编程和开发周期短的优势。

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彭卓
邓焱
马骋
熊剑平
尹永利
关键词 地震数据采集正弦信号发生器ΔΣ调制器现场可编程门阵列(FPGA)    
Abstract

A 24-bit sigma-delta digital-to-analog converter (DAC) is used to produce high precision sinusoidal signals with low total harmonic distortion (usually less than -106 dB) for seismic data acquisition system self-tests. The key problem is to convert the sinusoid to a sigma-delta bit stream to drive the sigma-delta DAC. This paper presents a field-programmable gate array (FPGA) based bit stream generator which is composed of a sinusoidal data memory, an interpolation filter and a sigma-delta modulator. This paper focuses on the design and simulation methods for the interpolation filter and the sigma-delta modulator and the whole system implementation using the DSP Builder in FPGA. Tests show that the bit stream generator can drive a 24-bit sigma-delta DAC to produce a 31.25 Hz, 3.96 V peak-peak voltage sinusoidal signal with -121.0 dB total harmonic distortion and 111.4 dB signal-to-noise ratio, which meets the needs for seismic use. The design is simple, programmable and easy to implement.

Key wordsseismic data acquisition    sinusoidal signal generator    delta-sigma modulator    field-programmable gate array (FPGA)
收稿日期: 2013-05-23      出版日期: 2015-04-16
ZTFLH:     
基金资助: 
引用本文:   
彭卓, 邓焱, 马骋, 熊剑平, 尹永利. 基于FPGA的高精度正弦信号发生器设计与实现[J]. 清华大学学报(自然科学版), 2014, 54(2): 197-201.
Zhuo PENG, Yan DENG, Cheng MA, Jianping XIONG, Yongli Yin. FPGA based high precision sinusoidal signal generator. Journal of Tsinghua University(Science and Technology), 2014, 54(2): 197-201.
链接本文:  
http://jst.tsinghuajournals.com/CN/  或          http://jst.tsinghuajournals.com/CN/Y2014/V54/I2/197
  位流生成器的结构框图
  数字插值滤波器结构
  3阶CIFB型ΔΣ调制器拓扑结构
参数
a1 0.125 722 395 773 830
a2 0.237 681 484 207 590
a3 0.201 902 444 368 128
b1 0.125 722 395 773 830
c1 0.288 682 654 030 458
c2 0.305 970 726 310 905
g1 0.000 295 309 968 229 897
  3阶CIFB型ΔΣ调制器参数计算值
  DSP Builder中的位流生成器硬件模型
  位流生成器模型的硬件模型仿真结果
  实测正弦信号发生器输出波形的频谱
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